1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a flash memory cell and a method of fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for improving the erase function and the topology of the memory cell.
2. Discussion of Related Art
Many studies have been made on semiconductor flash memory cells to fabricate highly integrated devices through simple processes. Related art has been disclosed in U.S. Pat. No. 5,070,032. In a conventional structure of a semiconductor flash memory cell, a device acts as an isolation layer as well. The isolation layer in this structure is formed by depositing an oxide layer on a buried data line. For example, cross-sectional views of a conventional flash memory cell in different directions are illustrated in FIG. 1. In a method of fabricating the conventional flash memory cell as shown in FIG. 1, a buried data line 18 having an n.sup.+ -type conductivity is formed on a semiconductor substrate 10 by ion-implantation. A high temperature and low pressure dielectric (HLD) layer and a device isolation layer (for example, an oxide layer) are then formed on the substrate 10 including the buried data line 18 to separate an active region from a field region.
Subsequently, a gate oxide layer 11 and a first polysilicon layer are formed on the entire surface of the substrate and then patterned to form a floating gate 12. The floating gate 12 is insulated by an oxide layer formed by oxidation. A second polysilicon layer is deposited on the entire surface of the substrate and then patterned to form a control gate 13.
The control gate 13 is insulated by a first insulating layer. A third polysilicon layer is deposited thereof and patterned to form an erase gate 14. A second insulating layer is further deposited on the entire surface of the substrate. Accordingly, gates and contact holes are formed at portions for desired contact points. Thereafter, the flash memory cell is completed by forming a passivation layer 16 of boronphosphosilicate glass (BPSG) on a metal line 15.
In programming the aforementioned flash memory cell, a high voltage is applied to the control gate and the data line, and electrons are injected into the floating gate at the edge of the gate insulating layer. To erase the programmed data in the flash memory cell, the electrons in the floating gate are removed through the insulating layer between the floating gate and the erase gate.
However, in the conventional flash memory cell, planarization of the memory cell is very difficult because of a step coverage generated by an erase gate formed on a device isolation oxide layer. Moreover, complex etching and plug processes are necessary to form the erase gate.